module rb16(clk, reset, writeD, regA, regB, regD, valueA, valueB, valueD);
	input clk, reset, writeD;
	input[2:0] regA, regB, regD;
	input[15:0] valueD;

	output[15:0] valueA, valueB;
	
	reg[15:0] regBank16x8 [0:7];
	
	assign valueA = regBank16x8[regA];
	assign valueB = regBank16x8[regB];
	
	always @ (negedge clk)
	begin
		if (reset==1) begin
			regBank16x8[0] = 0;
			regBank16x8[1] = 0;
			regBank16x8[2] = 0;
			regBank16x8[3] = 0;
			regBank16x8[4] = 0;
			regBank16x8[5] = 0;
			regBank16x8[6] = 0;
			regBank16x8[7] = 0;
		end
		else if (reset == 0 && writeD == 1) begin
			regBank16x8[regD] <=  valueD;
		end
	end
	
endmodule

module rb32(clk, reset, writeD, regA, regB, regD, valueA, valueB, valueD);
	input clk, reset, writeD;
	input[2:0] regA, regB, regD;
	input[31:0] valueD;

	output[31:0] valueA, valueB;
	
	reg[31:0] regBank32x8 [0:7];
	
	assign valueA = regBank32x8[regA];
	assign valueB = regBank32x8[regB];
	
	always @ (negedge clk)
	begin
		if (reset==1) begin
			regBank32x8[0] = 0;
			regBank32x8[1] = 0;
			regBank32x8[2] = 0;
			regBank32x8[3] = 0;
			regBank32x8[4] = 0;
			regBank32x8[5] = 0;
			regBank32x8[6] = 0;
			regBank32x8[7] = 0;
		end
		else if (reset == 0 && writeD == 1) begin
			regBank32x8[regD] <=  valueD;
		end
	end
	
endmodule

module srb16(clk, reset, writeD, regA, regD, valueA, valueD, callSys, retSys, pc, pcUp, typeCallSys, TLBAdress, interrupts, system);

	input clk, reset, writeD, callSys, retSys;
	input[2:0] regA, regD;
	input[15:0] valueD, pcUp, typeCallSys, TLBAdress;

	output[15:0] valueA, pc;
	output interrupts, system;
	
	reg[15:0] regBank16x8 [0:7];
	
	wire[15:0] tmpS7Out;
	reg[15:0] tmpS7In, pc;
	
	assign valueA = regBank16x8[regA];
	
	assign tmpS7Out = regBank16x8[7];
	
	assign interrupts = tmpS7Out[1];
	assign system = tmpS7Out[0];
	
	
	always @ (negedge clk)
	begin
	
		if (reset==1) begin
			regBank16x8[0] = 0;
			regBank16x8[1] = 0;
			regBank16x8[2] = 0;
			regBank16x8[3] = 0;
			regBank16x8[4] = 0;
			regBank16x8[5] = 0;
			regBank16x8[6] = 0;
			regBank16x8[7] = 0;
		end
		else if (reset == 0 && callSys == 1) begin
			regBank16x8[0] <= regBank16x8[7];
			regBank16x8[1] <= pcUp;
			regBank16x8[2] <= typeCallSys;
			if (typeCallSys[4] || typeCallSys[5]) begin
				regBank16x8[3] <= TLBAdress;
			end
			pc = regBank16x8[5];
			tmpS7In = regBank16x8[7];
			tmpS7In[1] = 0;
			tmpS7In[0] = 1;
			regBank16x8[7] <= tmpS7In;
		end
		else if (reset == 0 && retSys == 1) begin
			regBank16x8[7] <= regBank16x8[0];
			pc = regBank16x8[1];
		end
		else if (reset == 0 && writeD == 1) begin
			regBank16x8[regD] <=  valueD;
		end
		
	end
	
endmodule

